Simulation of in-memory logic circuit based on probabilistic memristor using LTSPICE

Abstract

Memristors are passive components with a varying resistance that depends on the previous voltage applied across the device. However, limited endurance of memristor devices and variations (both cycle-to-cycle and device-to-device) are important parameters to be considered in the evaluation especially in memristive logic families. There are a lot of factors on memristor variability, such as the influence of temperature, influence of switching the pulse parameters, influence of the concentration of oxygen vacancies, active dielectric layer structure and thickness as well as the influence of the parameters of conducting cell electrodes. In this work, only cycle-to-cycle variation is focus on both the deterministic and probabilistic behaviour in a memristor is being simulated and compared using LTSPICE software. Knowm or Mean Metastable Switch (MMS) SPICE model is being used to present the behaviour of a memristor. Monte Carlo simulation is applied to show the probabilistic behaviour in memristor. In summary, the best practical for probabilistic memristor model is within 50% range in terms of these model parameters (VON, VOFF, RON, ROFF). Besides, the impact of variability of memristors on the performance at in-memory logic circuit using different logic design styles such as Memristor-Aided Logic (MAGIC) and Memristor Ratioed Logic (MRL) are being implemented and analysed based on a universal NOR gate. The performance analysis of implementation of both MAGIC and MRL is carried out with respect to the functionality and sensitivity after applying the fluctuation. In this work, MRL design style is more robust and less affect by the cycle-to-cycle variability.