An efficient march (5n) FSM-based Memory Built-in Self-Test (MBIST) architecture with diagnosis capabilities

Abstract

In deep submicron Systems-on-Chip, embedded memories are consuming a growing part of the die area. The manufacturing test of embedded memory is a critical stage in the SoC production process that screens out faulty chips and speeds up the volume production of new manufacturing technology. Memory Build-In Self-Test or MBIST is a standard mechanism to test the memory arrays and potentially detect all of the faults that may be present inside memory cells using an effective collection of algorithms. However, a massive number of memory cells wrapped by BIST logic can result in substantial overhead in wiring and gate area, and also a detrimental influence on memory performance. Therefore, new MBIST designs for advanced SoCs that address the challenges must be explored to reduce the overall cost of manufacturing tests. It is important to choose the appropriate level of algorithmic coverage and diagnosis for a range of array sizes. The March 5n algorithm proven the alternative form of March-based algorithm with better test length has achieved shorter test time than conventional MATS++ algorithms without penalizing the fault coverage. This memory testing algorithm and architecture suit the needs for fast array testing to get the products to market in the quickest fashion. However, the previous work is extendable for inversion coupling fault detection and repair support. Therefore, the March 5n architecture is utilized as the foundation in this project. An improved March 5n architecture is proposed to extend its properties in terms of fault coverage and diagnosis capabilities to allow memory failure analysis. Block of March algorithms, an address generator, data generator, diagnosis module, and redundancy logic are the components of the targeted BIST architecture. Extensive circuitry from the previous architecture will be implemented to achieve the goals. The additional logic will accumulate the fault information and its corresponding diagnosis results will report during the memory testing. Synopsys Electronic Design Automation tools (VCS, Design Compiler and Verdi) are utilized in synthesising and evaluating the performance in terms of speed, area, power and fault coverage. Several reports and waveforms are generated and simulated for evaluation. The outcome of this project has demonstrated that adding more logic can enhance the capability for diagnosis and enable redundant programming to replace the defective cell. Besides, the inversion coupling fault coverage using the March 5n is verified to be functioning as intended. Speed up of the redundant memory space allocation in a repair mechanism is achieved with the proposed architecture due to the ability to keep track of each failure signature of memory when tested. In comparison to earlier work, the improved architecture has generally enhanced maximum clock speeds by almost 8% and decreased power dissipation by about 6%. However, higher speed and functionality are obtained at the cost of 4% of the area overhead.