Reliability analysis of junctionless fin field effect transistor (JL-FinFET)

Abstract

When scaling down of transistors reaches below 20nm, the reliability of a device becomes more important due to the device’s needs to sustain its performance while also being able to endure reliability degradation effects. Junctionless Fin Field Effect Transistor (JL-FinFET) provides a solution for conventional MOSFET problems such as the short channel effects while displaying better performance. In this project, the two most notable reliability issues of MOSFET which is Negative Bias Temperature Instability (NBTI) and Hot Carrier Injection (HCI) will be analysed on the proposed device structure of JL-FinFET. The structure of the JL-FinFET was constructed using a 15nm gate length (Lg), the fin width and fin height used were 10nm while the doping concentration for the source and drain terminal for N-type and P-type were fixed at 1.5x1019cm-3. The work function for the N-Type and P-Type JL-FinFET were set to 4.6eV and 4.65eV respectively and the oxide thickness used for the structure was 1nm. An analytical study of JL-FinFET concerning the degradation of threshold voltage (ΔVth) and on-current (ΔIon) by varying different device parameters such as they will be carried out between before and after stress applications. The reliability test for the reliability issues were carried out by varying stress voltage of 1.2V to 2.5V for HCI and 1.8V to 3.0V for NBTI for a stress time up to 10,000 seconds. ΔVth and ΔIon are the difference of the threshold voltage and on-current before and after stress application. This project aims to provide data on the degradation mechanism of NBTI and HCI on JL-FinFET and therefore, predict the lifetime estimation up to 10 years of extrapolation of the JL-FinFET by using the power-law extrapolation method. This can be achieved by simulating the JL-FinFET’s device structure and applying stress tests on the proposed device. To analyse the degradation effect on the device, several sets of stress voltage will be applied to the proposed device; to the gate terminal to observe the NBTI degradation and to the drain terminal to analyze the HCI degradation. Results show when stress is applied to the drain or gate terminal the Vth will increase thus increasing the voltage to turn on the device which signifies degradation. As the stress voltage applied increased the Vth also increase, which exhibits the degradation process will be faster if a higher stress voltage is applied. Results obtained show for the stress voltage of 1.8V the change of the Vth shift was 41.45% for HCI while for NBTI at stress voltage -1.8V the Vth was 15.7% indicating a faster degradation rate for HCI compared to NBTI.