Optimization of progress parameters for lower leakage current in 10 NM finfet using taguchi method

Abstract

The scaling of conventional transistor according to Moore’s Law is predicted to reach its limitation in the future. The conventional transistor using silicon material particularly at nanoscale channel has experienced the short channel effect (SCE), which leads to increase in the leakage current. Therefore, alternative device structure and advanced material are needed to overcome the SCE and reduce the leakage current (Il e a k ) with regards to the transistor performance. In this project, a method to control the leakage current in ultranarrow 10 nm FinFET using High-K dielectric material is proposed. The device’s fabrication and electrical characterization are then executed using TCAD Sentaurus from Synopsys. Optimization of the process parameters using L9 Taguchi method and finally prediction of the best combination of process parameters in order to obtain the minimum leakage current ( I l e a k ) in the 10 nm FinFET. There are four process parameters were varied, which are the fins dimension (fin height and width), channel concentration and oxide thickness. Smaller-the-Better (STB) Signal - to -noise ratio (SNR) and the Analysis of Variance (ANOVA) is used to study the performance characteristic and finally obtain the best combination of process parameters in order for the device to perform at its best performance, that will later benchmarked with predicted data from International Technology Roadmap for Semiconductors (ITRS) and previous published results. The optimization is expected to result in the attainment of the lower leakage current value in order to increase the speed performance of the device.