Design and characterization of 8×1 photon counting array in 0.13 μm CMOS technology at 1 GHz

Abstract

A single-photon avalanche diode (SPAD) is widely used as low-intensity ionizing radiation sensor at high speed detection rate application. The SPAD function when applied reverse bias voltage higher than the breakdown voltage of the device known as Geiger-mode. SPAD operates when the detected photon carrier activates a large avalanche current flow in a short period of time due to the impact of ionization. This avalanche effect occurs when the electrons or holes accelerated to high kinetic energies through a large potential gradient. This project focuses on the design and simulation of 8×1 passively quenched Single Photon Avalanche Diode (SPAD) array applying 0.13 µm CMOS technology. In term of fabricating the device, difference shape and size will have different current, voltage and count rate performances. Mentor Graphics TCAD is used to predict the performance of suggested SPAD array prior fabrication process. A SPAD is required to have high photo detection rates, high output signal in response to photons and faster counting speed. The drive for this project is to improve the counting rate of the model at low voltage and study the effect of quenching circuit integrated with SPAD. As the increasing demand of high-speed photon sensor, this design introduces a high-speed photon detection with quenching circuit applicable for several application as such biomedical, astronomy, fluorescence decay etc. In this project, Single Photon Avalanche Diode (SPAD) simulation model is utilized into 8×1 photon counting array circuit using 0.13 µm CMOS technology, to implement parallel detection and serial output of 8×1 photon counting array in 1 GHz counting rate and to characterize 8×1 array with non-time correlated timing. The 8×1 SPAD array designed using 0.13 µm CMOS technology via Mentor Graphics TCAD tool. The design is formed by integrating a single pixel SPAD from previous research into 8×1 array circuit and will provide an operation of parallel in serial out (PISO) result. In the single pixelate design, consist of the photon avalanche diode (SPAD), a passively quenching circuit and pulse discriminator circuit (PDC). The simulated dead time result from the schematic design for the 8×1 passive quenched SPAD array is observed with the result as 1 GHz operating frequency with the transistor size length 0.13 µm and width 0.35 µm. The result from physical designed layout is compared to the schematic design to ensure both designs provide the similar output.