Design of a lan interfacing module for a softcore processor AMIR CPU

Abstract

An AMIR CPU is a novel 32-bit softcore processor developed from the improvement of the weakness of existing Intel x86 and ARM architectures which has its own local I/O memory and easier ISA (Instruction Set Architecture) compared to RISC (Reduced Instruction Set Computer) and CISC (Complex Instruction Set Computer). The motivation of this project is to design a LAN interfacing module which is compatible with the features having by the softcore AMIR CPU. This is because the new AMIR CPU is not supported by HDL coding style but need to use its instruction set architecture to generate the machine code before can be implemented onto the FPGA. Besides this, this project is to study the capability of AMIR CPU to support the functionality of Ethernet communication as for now the development of this softcore processor is still in progress. However due to the reason of using a readyto- use Ethernet LAN controller, it is found out that the relative researches or resources are less whereby most of the research is based on C-based microcontroller that comes along with the ready-to-use Ethernet library. Therefore, the objectives this project are: (1) To build a SPI module on DE0 FPGA board in order to build up the same communication interface with the ENC28J60 (2) To send an Ethernet packet from DE0 to PC through the Ethernet communication with data transmission rate of 10MB/s using HDL coding style (3) To process the input data and send to PC through Ethernet by using AMIR instruction set architecture after the first two objectives are achieved. The scopes of the project are discussed in the section later. The project is aimed for contributing to develop the new feature (LAN) that able to work along with the new processor AMIR CPU and to study the methodology of establishing LAN that is different from the existing research.