Register-transfer level design of sum of absolute transformed difference for high efficiency video coding

Abstract

High Efficiency Video Coding (HEVC) is the state-of-the-art video coding standard which offers 50% improvement in coding efficiency over its predecessor Advanced Video Coding (AVC). Compared to AVC, HEVC supports up to 33 angular modes, DC mode and planar mode. The significant rise in the number of intra prediction mode however has increased the computational complexity. Sum of Absolute Transformed Difference (SATD), a fast Rate Distortion Optimization (RDO) intra prediction algorithm in the HEVC standard, is one of the most complex and compute-intensive part of the encoding process. SATD alone can takes up to 40% of the total encoding time; hence off-loading it to dedicated hardware accelerators is necessary to address the increasing need for real-time video coding in accordance with the push for coding efficiency. This work proposes a Verilog-described N × N SATD hardware architecture which is based on Hadamard Transform. The architecture would support a variable block size from 4 × 4 to 32 × 32 with 1-D horizontal and 1-D vertical Hadamard Transform. At the same time, it is designed to achieve throughput optimization by pipelining and feedthrough control. The performance of the implemented SATD is then evaluated in terms of utilization, timing and power.