Electrochemically deposited germanium on silicon and its crystallization by rapid melting growth

Abstract

It is well known that continuous miniaturization of transistors tends to create several problems such as current leakage, short channel effect, etc. Therefore, introduction of new channel material with higher carrier mobilities such as Germanium (Ge) is suggested to overcome this physical limitation and also to improve the performance of conventional transistors in chips. Basically, there are several techniques to grow Ge such as Chemical Vapour Deposition (CVD) and Molecular Beam Epitaxy (MBE) system. However, these processes require high vacuum environment, highly depend on such hard-to-control variables as well as costly. Therefore, an alternative method that practically cheaper to grow Ge utilizing electrochemical and rapid melting technique is investigated here. In this thesis, a systematic study of electrochemical deposition of Ge on Silicon (Si) substrate is outlined. Results show the unwanted Germanium Dioxide (GeO2) tends to form in the air-exposed process and germanium tetrachloride:dipropylene glycol (GeCl4:C6H14O3) electrolyte. Therefore, a Nitrogen (N2) controlled ambient is preferable. The uniform amorphous Ge film on Si (100) substrate was successfully obtained at the optimum current density of 20 mAcm-2 in germanium tetrachloride:propylene glycol (GeCl4:C3H8O2) electrolyte. Crystallization of electrodeposited Ge on Si (100) was demonstrated by rapid melting process. Effect of different annealing temperatures from 1000 to 1100 oC has also been studied. Raman spectra and Electron Backscattering Diffraction (EBSD) result confirmed that the grown Ge was highly oriented with the crystal orientation identical to that of Si (100) substrate at all annealing temperature tested. Based on depth profile from Auger Electron Spectroscopy (AES) measurement and Raman spectra, it was found that Si-Ge mixing occurred upon rapid melting process, particularly at near the Si-Ge interface caused by atoms diffusion. Calculated Si fraction diffused into Ge region in the Si-Ge mixing was high at higher annealing temperature that shows good agreement with solidus curve of Ge-Si equilibrium phase diagram. Correspondingly, the amount of Ge diffused into Si region also increased as annealing temperature increased. The result also shows that the tensile strain turns from high to low with the increase of annealing temperature. In addition, it drastically becomes more compressive as the depth is approaching the interface of Ge and Si. The difference in thermal expansion coefficient is a possible cause to generate such strain behaviour. For applications, the presence of strain in channel will improve the transistor performance by enhancing the carrier mobility. In conclusion, this study proves that electrochemical deposition and rapid melting growth technique are promising methods for synthesizing crystalline Ge and significantly contribute to the improvement of carrier mobility. It is expected that high performance Complementary Metal Oxide Semiconductor (CMOS) transistor scaling and Moore’s Law will continue in the future through new materials introduction in the transistor structure and by incorporating significantly appropriate levels of strain and composition of Ge/Si in the channel.