Speed enhancement on a matrix inversion hardware architecture based on Gauss-Jordan Elimination

Abstract

Matrix inversion is a mathematical algorithm that is widely used and applied in many real time engineering applications. It is one of the most computational inten-sive and time consuming operations especially when it is performed in software. Gauss-Jordan Elimination is one of the many matrix inversion algorithms which has the advantage of using simpler mathematical operations to get the result. This work presents the architecture of a matrix inversion hardware using Gauss-Jordan Elimina-tion algorithm with single precision floating point representation. The proposed design is an enhancement of a previous work which implemented Gauss-Jordan Elimination to perform matrix inversion for complex matrix suitable for MIMO applications. The proposed design was bench-marked with other implementations such as hardware ar-chitecture of similar matrix inversion algorithm, hardware architecture of other matrix inversion algorithms and software implementation such as C++. The execution timing performance of the proposed design is improved in comparison with the previous ar-chitecture design by a factor of 0.14 for a matrix size of 36x36. Overall, the proposed design is capable of preforming matrix inversion for a matrix of size 36x36 in 1.9 milliseconds and consumes hardware resources of about 18128 logic elements.