Enhancing SRAM performance of common gate FinFET by using controllable independent double gate

Abstract

This project is focus on the research and evaluation on the characteristic of independent controllable gate FinFET structure in static random access memory (SRAM) circuitry. BSIM-CMG model for common gate FinFET is chosen in this research. The independent controllable gate FinFET is constructed using two parallel connection of common gate FinFET except the gate terminal, thus it has the independent controllable gate capability. SRAM 6T scheme is being chosen in this study and benchmarking with the conventional common gate FinFET SRAM. Netlist for device NMOS and PMOS, and the SRAM circuitry are being constructed and simulated with HSPICE tool. From the device perspective, through the dynamic gate voltage adjustment capability, the IV characteristic of this proposed structure has better drive currents with 1.1X for NMOS and 1.3X for PMOS compare to conventional common gate FinFET. Besides that, there is a significant reduction of leakage current in this proposed structure compare to the conventional common gate FinFET, the reduction leakage for NMOS and PMOS is up to 3 order magnitude. The results of the SRAM circuitry constructed by this proposed independent controllable gate FinFET structure has shown that the read and write margin are higher than the conventional common gate FinFET SRAM design. Besides that, the proposed structure in SRAM design is beneficial to low power application design as it has lower standby current. Furthermore, different back gate bias scheme for this structure is explored, and the optimum back gate scheme is proposed which having the reverse biased on Pull Down device and Pull Up device, with the dynamic gate voltage control on the Pass Gate device.