Network-on-chip floorplanning and application mapping using cross-entropy method

Abstract

The increase in number of on-chip components (IP core) integration on System on Chip (SoC) has caused the communication of on-chip components (IP core) to hit the bottleneck of communication due to bandwidth limitation of buses. Networkon- Chip (NoC) is introduced to solve the communication bandwidth problem and it is widely used in System-on-Chip (SoC) nowadays to enable the communication between on-chip components through routers and network channel within the chip so that the complexity of communication between on-chip components can be reduced by reducing number of wire used which can lead to huge saving in chip area and reducing dynamic power significantly. The performance of Network-on-Chip (NoC) is highly dependence on floorplanning methodology used which can improve performance (transfer rate) of Network-on-Chip (NoC) blocks while meeting communication requirements and achieving minimal area overhead. The Cross-Entropy (CE) method has been applied successfully by researcher in various optimization problems and able to produce promising results. Therefore, the Cross-Entropy (CE) Method is introduced to solve optimization problems for Network on Chip (NoC) floorplanning and application mapping. The Cross-Entropy (CE) method is used to generate optimal floorplan with optimal communication cost for various multimedia benchmark applications. Evaluation results show that the Cross-Entropy (CE) method is able to produce comparable results compared to other selected methods from published journal papers and has faster convergence in terms of iteration/generation when compared to GA with heuristic crossover and random initial mapping.