Modeling and simulation of graphene three branch junction using verilog-A

Abstract

Graphene three-branch junction device (G-TBJ) is a non-conventional device that offers promising potential in various application in digital (e.g. logic gates) and analog (frequency mixer, etc) circuit. Operation of G-TBJ can be explained by a capacitor-based equivalent circuit. However, the proposed equivalent circuit neglects other device parameter and properties which can affect the characteristics of G-TBJ. The main objective of this project is to investigate other device model consist of graphene field effect transistor (G-FET). The feasibility of implementing of embedded Verilog-A models to simulate TBJ was assessed. The device simulation is performed using Quite Universal Circuit Simulator (QUCS). First, simulation results of single G-FET is verified against with result measured from fabricated GFET in experiment. Next, simulation is done at TBJ circuit level where two G-FET devices are connected at two terminals. Simulation result shows that model which is proposed and implemented in verilog-A has produced a close result with experiment and simpler device physics formula to describe the operation principle of GFET. Thirdly, TBJ is simulated as inverter. The inverter shows voltage gain of 0.0065 at voltage supply of 0.1V.