FPGA implementation a reconfigurable address generation unit for image processing applications

Abstract

Nowadays, the DSP algorithms are being widely used in the world of digital image processing. Example of the DSP algorithms that used in image processing is 2D correlation, 2D convolution, fast Fourier transforms, FIR filter and etc. The performance of the DSP algorithm is highly depends on its processing speed and memory bandwidth. Those algorithms require intensive data manipulation and calculation happens in parallel. The DSP algorithms also require complex address pattern calculation. The DSP processor needs to handle the data processing and also complex address calculation in the same time. The complex address pattern calculation using RISC processor is not efficient and therefore slower down the overall memory access speed. Hence, a dedicated hardware blocks to perform the address generation is essential. Such hardware known as Address Generation Unit(AGU). The prior arts of AGU have limitations as some of the AGU do not able to handle image edge condition and data reuse. Besides that, the prior art of the AGU have not been verified in the actual SOC environment. In this project, a reconfigurable AGU that targeted for 2D correlation, sum of absolute difference and Finite Impulse Response (FIR) is proposed. The proposed AGU able to take care of the image edge conditions by padding it with edge pixels. The proposed AGU also being integrated into the Altera Avalon fabric and fully verified in Altera DE2-70 FPGA. It also shows 30% to 40% improvements in the performance at certain area.