Gradient image generator hardware/software co-design

Abstract

This project proposes a software and hardware architecture for computing image gradients in order to reduce the input image size. The only way to transfer data in real time using lower speed wireless communication systems is to reduce the frame size; if a 24bit image is binarized the size will be reduced 24 times. In this project the Canny algorithm is analyzed and written in Matlab and C programming language for NiosII CPU. Then it is implemented in a Field Programmable Gate Array (FPGA) hardware and the timing result for every step is measured. Based on these timing results, a final co-design is proposed. The output image after processing is a binary image that is at least 24 times smaller than the original image. For a sample 98�183, 24bit image and a working frequency equal to 50MHz, total logic elements for final co-design increased about 4 times of software design, but execution time in co-design architecture is 19 times faster than software. The hardware implementation in this paper is done on Altera CycloneII FPGA board.