Gate leakage logic detection for analog CMOS circuit

Abstract

In micron technology node, Igate is not a big issue to circuit designer due to its negligible value. But in deep submicron technology node, Igate is one of the major and dominant leakage components. Igate is also reacts to process variation. As this issue arise, circuit designer need to aware the impact of Igate towards their design. In addition the ability to observe the Igate level is more desirable. The variation in Igate is most sensitive to oxide thickness, TOX, due to their exponential relationship (Mukhopadhyay and Roy, 2003). It will rise by the factor of 4,000 from 90 nm to 50 nm node (Helms, Schmidt and Nebel, 2004). TOX tends to vary from one process corner to another, resulted in the variation in Igate. In digital circuit, Igate will contribute to increase off state power consumption. In contrast, for analog circuit, simple current mirror with large ratio will suffer on unexpected output current due to the leakage path from gate to ground.