Register transfer level design of compression processor core using verilog hardware description language

Abstract

Throughput independent and parameterized data compression processor core was designed to tackle the needs of high-speed data compression applications. The design is based on combination of LZSS algorithm and Huffman coding, which enables it to be used in compression of a wide variety of data types. However, several design limitations exist. The design uses several technology-dependent modules that limit its hardware realization in alternative technologies. In addition, it also suffers from an abnormal functional behavior when trying to decompress data that contain sufficiently high redundancy. In view of these limitations, design enhancements are proposed. One of the proposed enhancements is to improve the design portability to any hardware implementation technology. This is accomplished through designing generic hardware to replace the technology-dependent modules and utilizing conditional compilation approach to best decide the design realization given the available resources and constraints. With this approach, IP cores designed for the targeted technology should be used to take advantage of the efficient resource utilization and proven design, which leads to faster time-to-market and minimizes the integration risks and verification efforts of large systems. However, if the design does not have access to IP cores, then generic modules can be instantiated but at the expense of development cost. Another design enhancement offers a hardware patch to fix the decompression core hardware bug. The issue was identified to originate from writing and reading the same memory location simultaneously. As a solution, the behavior of the memory controller and its supporting logic are modified to prevent this from occurring. From the design simulation results, it is concluded that the decompression core hardware bug is finally solved.