Fast fourier transform module for implementation in Nios II embedded processor

Abstract

The Fast Fourier Transform is an indispensable algorithm in many digital signal processing applications but yet is deemed computationally expensive cost when designed it on hardware. This thesis proposes a design and implementation of Fast Fourier Transform algorithm in embedded system by utilize it in Nios II embedded processor and integrate with Nios II floating point custom instruction. The design is based on Decimation-In-Time and Decimation-In-Frequency radix-2 for the better performance and speed. Hardware implementation, the ALTERA CYCLONE II EP2C35F672C6 (DE2 board) is used. Hardware interfacing, Graphical User Interface (GUI) has been developed using MATLAB software; it’s an original method for interfacing between ALTERA Field Programmable Gate Array (FPGA) and software in host PC. Input values are sent from MATLAB to ALTERA development board via serial port and the calculation data return back to MATLAB. The purpose of this technique is take advantages of the MATLAB in analysis and plot the result.