Thermal-safe system-on-chip test scheduling using dynamic voltage and frequency scaling

Abstract

Designing integrated circuits (ICs) has become more challenging when fabrication technology scales down. Overheating has been acknowledged as a major issue in testing due to high power consumption of a chip during test. A direct consequence of the increasing power density is the increasing junction temperature that poses several problems such as aging issue. Therefore, thermal estimation needs to be considered during test scheduling to avoid exceeding temperature limit of the System-on-Chips under test. This thesis proposes a new thermal model that considers metal layer effects of SoC, and thermal safe test scheduling with dynamic voltage and frequency scaling (DVFS) technique. The difference in estimated temperature is over 10 °C if the effect of metal interconnect is neglected. In DVFS, the energy savings obtained by eliminating the global clock are, in many cases, offset by the additional power consumed due to longer execution time. The thermal safe test scheduling problem is formulated as a combination optimization problem, and the integer logic programming is used to find the optimal solution of test schedule for a given SoC under thermal constraint. The proposed thermal model is a necessary tool for rapid thermal analysis of the system which is exposed to non-uniform substrate temperature including thermal effect from metal interconnects. This thermal model will be used to estimate temperature during test scheduling in order to optimize total test time under thermal constraint. Results on different benchmark SoCs have shown the effectiveness of the proposed technique which produces shorter testing time. Total test time reduction by using the proposed technique is 46% compared to conventional existing techniques. Overall, the proposed technique produced more effective thermal aware test scheduling.