Damage mechanics-based model for reliability assessment of through-silicon via interconnects

Abstract

Through-silicon via (TSV) is one of the emerging technology enablers for the 3D Interconnects. TSV configuration consists of conductive materials, such as copper or tungsten, dielectric liner, which is silicon dioxide and silicon as the semiconductive material. The difference in thermal expansion rates between those integrated materials will cause accumulation of plastic strain at the interface of Cu/SiO2 during the operation. The research aims to develop a damage mechanicbased model for reliability assessment of through-silicon via interconnects. During thermal excursions, extensive plastic strain is likely to form between materials with different coefficients of thermal expansion. It leads to the accumulation of voids and subsequently, fracture occurs in the critical section. In this development, the response of Cu coating with a thickness of 8 p,m in a typical package with TSV interconnects is examined. Finite element (FE) analysis is employed along with experiments and published experimental data in establishing a thorough understanding of the mechanics and failure processes of copper interconnects. The accuracy of FE results of TSV model is greatly dependent on the behaviour prescribed for the Cu interconnects in the analysis. In this respect, the Johnson-Cook constitutive equation is employed with the material model constants extracted from a series of nanoindentation test data at different displacement rates. The temperature-dependent data are obtained from published nanoindentation test results at varying temperatures. The TSV Interconnects subjected to temperature cycles are examined. Material parameters for cyclic properties are established based on published data on copper coating cyclic test. Johnson-Cook Damage model was utilized to demonstrate the damage characteristic of metallic vias. The FE model is then used to perform the design sensitivity analysis of the TSV. It was found that the plastic strain-based damage model adequately predicts the damage and fracture processes of Cu-filled via under temperature changes. Based on the design sensitivity analysis, the minimum radial stress magnitude for TSV array with 15 and 20 (jrn pitch length is lower than the threshold keep-out-zone (KOZ) stress of an- = 69.6 MPa. Thus, the staggered array o f 5 [un-diameter TSVs with pitch lengths of 15 and 20 jxm could accommodate transistor devices without adversely affecting its performance.