Integrated circuit design of a multiplier-accumulator for convolutional neural network based on carry-save adder architecture

Abstract

Convolutional Neural Networks (CNNs) are hierarchical biologically-inspired models that may be taught to perform a variety of detection, identification, and segmentation tasks. The key processing requirements in the CNNs process are the multiplier-accumulator (MAC) operations in the convolution layer. A perfect fusion of various multipliers and adders would yield an ideal MAC for CNNs' convolution layer. Besides this, different kernel mask sizes are required throughout the convolution layer in CNNs, depending on demand. In general, each size of kernel mask requires a unique MAC architectural configuration, thus lengthening the time spent in research and development. To overcome this problem, a flexible MAC design has been developed that allows users to choose between different sizes depending on the requirements of the CNNs. This method, known as Selective Kernel Size, may activate kernel sizes from 1x1 to 7x7. This thesis also proposes a new MAC architecture called Mulitplier- Accumulator with Carry-Save-Adder (MACcsa ) to improve the MAC performance by efficiently computing the sum of three or more bits of input. Each proposed design is synthesized to Silterra 180 nm technology, and the time, power consumption, and cell area are all compared. Selective Kernel Size architecture demonstrates a substantial gain in terms of cell area and power from 56% to 80% when compared to mixing different sizes of MAC design in specific CNNs network, with some degradation in time delay. When comparing the classical addition structure to the proposed MAC with the CSA structure, results show that while the MAC with CSA is only slightly faster than the classical MAC, the power and cell area are improved by 4% to 10%.