Modelling and simulation of Heteromaterial Dual-Gate Dopingless TFET (HTDGDL-TFET) and its application as digital inverter

Abstract

Tunnel Field -Effect Transistor (TFET) has been known as one of the promising devices which will be replacing Conventional Metal Oxide Semiconductor Field-Effect Transistor (MOSFET) as a future low-power and high-speed logic application. This is because as the size of MOSFET reduce decade by decade, to achieve better speed and lower power, and currently moving towards the nanometer regime, has leads to the limitation of the performance of MOSFET. These few bottlenecks such as increasing of leakage current, Short Channel Effects (SCEs) and complexity in device fabrication have been faced while scaling down the size of MOSFET. Therefore, TFET which work on principle of tunnelling phenomenon has been proposed as one of the devices to replace MOSFET which work on the principle of thermionic emission that limits the device’s sub-threshold swing to 60mV/decade. TFET has various of features such as immunity from most of the Short Channel Effects, lower leakage current, lower sub-threshold swing which is below 60mV/dec, lower threshold voltage and higher OFF current over ON current ratio. However, there are also some drawbacks for TFET such as complexity of fabrication process in doped TFET which cause various defects. These can be overcome by using dopingless technique. This technique helps in producing defects-less and more economical devices. Another drawback would be TFET exhibits lower ON state current. Heteromaterial TFET can be used to solve the low Ion issue. To have a better controllability of heteromaterial TFET channel, dual gate is proposed. Sub-threshold swing (SS) is one of the important parameters to determine a device performance. By lowering the SS, the device performance will be better in term of lower leakage current, better Ion/Ioff ratio and lesser energy. There are 3 objectives for this project: To model and simulate Heteromaterial Dual-gate Dopingless TFET (HTDGDL-TFET). To compare the performance of TFET between Ge, Si and GaAs as Source region material. To apply the HTDGDL-TFET as a Digital Inverter. This project will be simulated using Silvaco TCAD tool. Single-Gate and Double-Gate HTDL-TFET has been successfully modelled. 4 simulation test cases have been done for this project to select the best structure of proposed TFET. Several important parameters such as Vth, SS, Ion, Ioff and Ion/Ioff ratio are used to measure the performance of TFET. Among all of the 4 test cases, the best TFET structure is with Ge as source region material, source and drain region carrier concentration of 1×1019 cm−3and channelcarrier concentration of 1×1017 cm−3and dopingless. This is because the deviceshows Vth value of 0.97V, SS value of 15mV/dec, and Ion/Ioff ratio of 7×1011. Thepropagation delay for designed TFET inverter is 75 times shorter than the inverter from [21]and is 29 times shorter than the market inverter [SN74AUC1G14DBVR]. Somefuture works also have been suggested in this thesis.