Area-optimal cache coherent protocol for many-core network-on-chip

Abstract

Cache coherence support is a major component in network-on-chip (NoC) systems which consist of multiple processing cores or elements as it is essential to ensure that the changes in shared memory are well communicated between all cores. Due to the nature and architecture of NoC, cache coherence protocols can have different characteristics in terms of various design consideration factors such as performance, area and power. Since the number of cores are expected to increase more in computing systems in the future, these factors need to be appropriately considered for scalability during design process so that the implementation will be feasible and be able to maintain an effectiveness of the system design. Cache coherence protocols proposed for NoC systems such as the directory protocol, Hammer and token protocol each has different impact on execution performance and design cost associated, due to the different mechanism used to maintain the cache coherency. In this project, these protocols are implemented and simulated using the GEM5 simulator and the area overhead is estimated using the Multicore Power, Area, and Timing (McPAT) framework. The simulation using blackscholes, fluidanimate and bodytrack application from the Princeton Application Repository for Shared-Memory Computers (PARSEC) benchmark shows that the Hammer protocol outperforms all evaluated protocols in execution performance, but the area overhead required for the protocol is also the largest. Token protocol, on the other hand, provide a significant lower performance, which is 2% lower compared to the Hammer protocol, but its 7% area overhead incurred is the lowest among all protocols. This shows that token protocol exhibits the best scalability for area overhead with increasing number of processing cores while providing moderate performance in terms of execution time.