Explicit charge-based model for strained-silicon gate-all-around mosfet including quantum and short channel effects

Abstract

In the recent development of advanced nanoelectronic devices, strain application on silicon Metal-Oxide-Semiconductor Field-Effect Transistor (MOSFET) has been identified as a key factor towards the improvement of device performance. Strainedsilicon is preferred due to less impact of the short channel effects, enhanced the carrier mobility and lower the threshold voltage . Besides, strained-silicon can be applied to the non-planar multi-gate structures such as Gate All Around (GAA) MOSFET. Chargebased modelling (Qm) technique is widely been used for unstrained GAA MOSFET. However, in this research work, the approach is exercised for strained-silicon GAA MOSFET and subsequently to characterise its electrical behaviour in long and short channel devices. The model is solved explicitly using a smoothing function to avoid the convergence issue compared to the numerical model. For one-dimensional (1D) strained silicon GAA MOSFET, the geometry scaling in the radial direction which includes the radius and oxide layer thickness of the silicon layer can contribute to the quantum effects. In order to improve the accuracy of the model, quantum capacitance and threshold voltage were integrated into the long channel explicit model to facilitate the quantum effect. For the short channel model, second-order physical effects were included such as velocity saturation, channel length modulation and threshold voltage roll-off to resemble the behaviour of the short channel device. Afterwards, the results from the constructed models are compared against the Technology Computer Aided Design (TCAD) simulation and published data. A good agreement was achieved between model and simulated data indicates that the physical mechanisms of quantum and short channel effects used in the model are valid. Besides, it is shown that the existence of quantum starts to exhibit for radius and oxide layer less than 10 nm and 14 nm, respectively, regardless of the channel length being used in the device structure. For device optimisation, gate stack with SiO2�H fO2 configuration is preferred due to its smaller leakage current. The most optimised dimension is attained with the gate length of 40 nm attributed to the enhanced overall electrical performances. The extracted threshold voltage and on-state current obtained as 0:164 V and 8000 uA/um, accordingly, where the values outperform the IRDS benchmarking for low power application device.