Asic implementation of low latency montgomery modular exponentiation

Abstract

Nowadays, electronic communication devices tend to design smaller in size, lighter in weight, lower in cost and higher performance. Individual may tend to use electronic communication devices when exchanging sensitive matters, such as personal details, contract documents, company secrets and specific passwords are sent to other parties. Since internet is one of the important key contacts and electronically communicates with billions of people, protection for the transmission of important messages over the internet is vital. Encryption plays a vital role for every user in ensuring security of communication within the organization. Hence the algorithms needed for safe communication. The motivation of this project is to protect digital data in computer confidentiality, as it is often stored on computer systems and distributed through the internet or other computer networks. Rivest-Shamir-Adleman algorithm is first introduced by Ron Rivest, Adi Shamir and Leonard Adelman in 1977, and it is known as one of the famous public key cryptography algorithms since it is an asymmetric cryptography. Besides, the theory behind RSA is relatively simple and easy for modification purpose as it relies on algorithm such as factorization and modular exponentiation. In this paper, the whole process and algorithm has been described for 256-bit key size. Due to the bit length of modulus, the work included different but suitable implementation, which is the basic, radix-4 and radix-16 implementations to reduce the speed of cipher-decipher process. Implementation on Verilog HDL using Vivado Design Suite software has been done. Enhancement on speed and delay is the main constraint of this project. According to the synthesis results, the radix-16 Montgomery Multiplier implemented in RSA cipher can be implemented with a nearly 60% reduction in encryption latency. However, radix implementation will involve more loop unrolling steps that resulted in a higher gate count. It is conceivable to absorb the increase in the gate count in the RSA cipher in return for performance as chip technology improves.