Characterization of nanosheet transistor logic and its performance

Abstract

Considering Moore's law requires transistor scaling, we have now entered the nanoscale era, which brings with it new challenges. Fin-shaped Field-Effect Transistors (FinFETs), the current transistor technology, is not up to the challenge when we descend below the 7 nm scale. The short channel effect downgrades the system performance and reliability as the MOSFET is scaled down further. For 5 nm technology node and beyond, nanosheet FET (NSFET) is an alternative architecture that compensates for this limitation due to superior short channel control at a smaller footprint. NSFET can give more effective width, and therefore current, by stacking nano sheet atop one another. In this project, the research gap and past efforts on showing the superiority of NSFET over FinFET were discussed. Using the Sentaurus tool from Synopsys, a three-stacked NSFET 3D structure with sheet thickness of 7nm was created and characterised. The NSFET is being build based on the parameters as per suggested from the reference. The simulation is being validated to the reference. This work is focus on the characteristic of a p-channel NSFET and the analog parameters of the NSFET. Simulation of the electrical characteristics for the NSFET includes current voltage characteristics and extract the electrical parameters such as threshold voltage (Vt), ON-current (Ion), OFF-current (Ioff) ON-OFF current ratio (Ion/Ioff), subthreshold slope (SS), transconductance (gm) and output resistance (Ro). The data collected to be utilised to develop NSFET circuits A p-type and n-type NSFET is being combined to build an inverter. Under the same footprint, NSFETs are expected to have superior current drivability and gate-to-channel controllability than FinFETs, resulting in higher intrinsic gain for circuit applications.