CMOS low noise analog front-end design for multi-lead non-contact electrocardiogram

Abstract

Since the early 1980s, cardiovascular diseases (CVD) has been the leading cause of death and the use of a wearable device to monitor patients could greatly impact the disease outcomes on healthcare systems. However, Malaysians still lack awareness towards the cardiovascular diseases even although cardiovascular disease is the top killer in Malaysia. Cardiovascular disease (CVD) remains the main cause of morbidity and mortality in the world and hence early cardiovascular disease detection is very crucial so that appropriate treatments and counselling can be done in the early stage. Over the past decade, the detection and analysis of biological electrical signals from the surface of the skin using non-invasive electrode has shown to be a powerful device for the diagnosis of clinical conditions. The wet bioelectrode which is using the reticulated gel foam is a universal standard bioelectrode utilized in clinical settings. However, in a long-term application, dehydration of the gel can cause the bioelectrode to become unstable and troublesome, and hence it can result in severe signal attenuation and noise interference. As a result, detection of bioelectrical potentials using non-contact method is desired for the long-term recording of heart biopotential signals. This work is focusing on designing an integrated front-end CMOS analog circuitry that is capable to detect heart electrical signal while achieving low noise circuit performance. An electronic interface to be used with multiple contactless electrodes has been studied in order to develop a wearable health device that able to perform several lead measurements compared to conventional one-lead system. Furthermore, the ability of the proposed interface to amplify differential biopotentials and to reject common-mode signals produced by electromagnetic interference are investigated as well. This work is implemented using Silterra 0.13 μm CMOS technology using Cadence computer-aided design tool. From the simulation result, the CMOS operational amplifier design achieved the gain of 64.2286 dB and phase margin of 83.3°. It also obtained CMRR of 89.9357 dB, PSRR of 71.6896 dB and a lower power dissipation of 3.5 μW at the operating frequency range between 0.05 Hz to 250 Hz. In addition, the complete interface with driven right leg circuit in this project is able to achieve gain more than 50 dB at the same operating frequency as well. This amplifier output will be eventually connected to other peripherals that will make up a whole ECG monitoring wearable health device.