Wirelength estimation in VLSI cell placement using machine learning techniques

Abstract

In recent years, artificial intelligence (AI) plays an important role in Very Large-Scale Integration (VLSI) circuit design for wirelength prediction of cell placement. As compared to conventional wirelength estimation techniques such as Half-Perimeter Wirelength (HPWL) and Rectilinear Steiner Minimal Tree (RSMT), wirelength prediction using AI does provide the results with higher accuracy within a shorter runtime. Therefore, this paper aims to implement and investigate the performance of several machine learning-based wirelength estimation models on the International Symposium on Physical Design (ISPD) 2011 circuit benchmark. Machine learning models such as Artificial Neural Network (ANN), Support Vector Machine (SVM) and Random Forest (RF), are introduced in this paper. Besides, this paper also targets to integrate the machine learning model with the best accuracy and runtime, into actual placement. The results indicate that RF is the best choice for replacement of conventional method as RF achieved an accuracy of more than 90% for wirelength estimation, and the runtime taken by RF is approximately 10000s much faster than RSMT.