Low latency cipher for hardware-based memory protection unit for application in system-on-chip root-of-trust

Abstract

The goal of trusted computing is to guarantee the behaviour of the software running on the devices. Memory Protection Unit (MPU) secures accesses between main memory, and caches which plays an important role in the System-on-Chip Root-of-Trust. There are several cipher algorithms such as SIMON, PRESENT, PRINCE, SPECK, and KATAN are suitable for MPU. These ciphers have been analyzed in different metrics such as area, power, throughput, latency, and others. Latency is one of the critical parameters that need to be considered when selecting the MPU cipher. The PRINCE algorithm has the lowest latency based on previous studies to fulfill the main MPU design requirement. The objective of this research is to synthesize and implement the PRINCE cipher architecture for the MPU to secure sensitive data exchange with an emphasis on low latency. For the hardware-based memory protection targeted for Field Programmable Gate Array (FPGA), the PRINCE cipher using three pipeline stage is designed at the register transfer level (RTL) using Verilog and verified by dynamic simulation using the Xillinx ISE. As the additional MPU structure between the main memory and cache increased the memory access latency, we validate the latency result based on memory performance model to quantify the overall performance with the additional five clock cycle encryption latency. The validation result for libquantum and gcc application showed 0.64% and 0.29% execution time overhead due to increased memory, respectively. Besides, the resource overhead decreased as pipeline design was implemented. The impact of additional latency cipher on the execution time has low significant on the overall performance and produced more impact if the Last Level Cache (LLC) miss ratio is high as libquantum application has higher LLC miss ratio compared to gcc application.