Design and implementation of lightweight encryption algorithm using prince cipher

Abstract

Lightweight cryptography is widely deployed on low-resource devices that has limited computing power, low memory size and power resource. With the rising of pervasive computing, more devices are connected online, and new requirement on encryption model that emphasizes on ultra-fast response time is introduced. Most of the available lightweight cryptographies are round-based designs, they are able to achieve high throughput via pipelining the round functions, however the response time is not ideal. The Prince cipher is the first lightweight block cipher developed to speed up the latency of the algorithm. Compare to other block ciphers, the Prince is able to yield low latency with very competitive area utilization, hence it is a promising choice for low-resource devices that emphasize of response time. In this work, the Prince cipher will be designed and synthesize in different implementation including roundper- cycle, single-cycle and reduced multicycle implementations. The synthesis results had suggested that the single-cycle Prince cipher is achievable with almost 40% reduction in encryption latency. This indicates the possibility of instantaneous encryption as the full operation can be performed within a single clock cycle and no warm-up phase is needed. However, the implementation using loop unrolling also introduced larger gate count and therefore the design will have bigger silicon footprint. With the improvement of chip technology, it is possible to absorb the increment in of the gate count in the Prince cipher in exchange for performance. Furthermore, the modern SOC design often involves many-core designs that have high-bandwidth, packet-switched network design. These applications need the data to be processed as fast as possible, hence the conventional high throughput looping approaches are not desirable as they might limit the bandwidth of these high-speed buses within the SOC.