Hardware acceleration of secure hash algorithm 3

Abstract

Secure Hash Algorithm-3 (SHA-3) is the most recent and efficient cryptography hash functions widely used in most information security applications. Contemporary, SHA-3 were built as software where the performance of the cryptographic function is based on the performance of the general-purpose CPU. Since SHA-3 is frequently used in requires multiple operations per data input and is generally inefficient running on a general-purpose CPU. To improve the performance of the SHA-3 function on data encryption progress, an alternative solution is to implement the SHA-3 algorithm as a hardware accelerator. The proposed accelerator is targeted at the most computation-intensive function in the C-based SHA-3 algorithm which is Keccakf that is executed 97.56% in an SHA-3 operation and synthesized using Xilinx’s Vivado High-Level Synthesis (HLS) to hardware implementations targeted for FPGAs. Besides, the proposed SHA-3 accelerator is employed in the architectural optimization approaches based on the concepts of loop pipelining, loop unrolling, and memory array mapping. Considering the trade-offs between the performance and hardware cost, the SHA-3 architecture in terms of the high throughput and less resource is identified. Incorporated with four-stage sub-pipelining and fully loop unrolling on five permutation steps, followed by memory array partitioning by factor of 25, new SHA-3 hardware architecture is proposed. The proposed SHA-3 accelerator is able to achieve up to 47.7Gbps throughput and operate up to 722.5 MHz. As compared to other existing works, the proposed SHA-3 implementation achieves high throughput performance and operation frequency at a reasonable cost.