8192 bit Rivest-Shamir-Adleman data encryption hardware accelerator

Abstract

Rivest-Shamir-Adelman (RSA) algorithm is one of the state-of-art publickey cryptography that is efficient in terms of implementation because it uses the same general equation for encryption and decryption, that is, modular exponentiation equation. The security reliability of RSA algorithm is based on the difficulty of factoring a large number. The larger the RSA key size, the higher the security level that can be achieved. However, at the same time, the complexity of the computation increases, which results in more computation cycles. Software implementation of RSA with large key size is too slow and less effective for large amount of data encryption or decryption. Hence, the purpose of this project is to implement a hardware-based RSA coprocessor to handle RSA encryption and decryption effectively. This project implements a RSA coprocessor using radix-2 Montgomery modular multiplication that described at bit-level. This implementation uses carry-saved adders to achieve parallel processing in hardware. The hardware implementation of the RSA coprocessor is done using Verilog synthesizable Register-transfer Level (RTL) code to allow scalability. Simulation results are obtained to validate the functionality of the design. The design is synthesized using Altera Quartus software tool to evaluate the performance of the implementation. The designs are synthesized on device Stratix V 5SEEBF45I4 for key-size of 128-bit, 1024-bit and 8192-bit. The data throughput of the 8192-bit design can reach up to 3.387 kbps with LE utilization of 30% on the device used. Although the performance of the design is not the highest among the related works, but this design provides a proven working prototype for 8192-bit RSA coprocessor using Bit-level Montgomery Modular Multiplication for hardware parallel processing.