Seven levels symmetric H-bridge multilevel inverter with less number of switching devices

Abstract

This paper proposes a new topology of a cascaded multilevel inverter that utilises less number of switches than the conventional topology. The proposed topology maintains the performance of conventional 7-levels output multilevel inverter while reducing the loss of power, installation area, converter size as well as development cost. The circuit development consists of six switches and one diode. With less number of switching devices in the circuit, there will be a reduction in the gate driver circuits and also in effect fewer switches required for specific intervals of time. Simulation works have been conducted to validate the proposed MLI topology. It is envisaged that the proposed topology can be applied for the system that requires high efficiency and a low electromagnetic interference.