The design of an FPGA-based sinusoidal pulse width modulation generator

Abstract

The output of a DC to AC converter circuit is not a pure sine wave. To overcome this problem, a technique called sinusoidal pulse width modulation (SPWM) is used. Generation of SPWM requires a carrier wave and a reference wave. The reference wave is typically a sine wave. Many algorithms have been proposed in the past to optimize the generation of the sine wave but the most suitable scheme uses a lookup table (LUT). In this project the SPWM is implemented using a field programmable gate array (FPGA) where discrete sine values are stored as lookup table in the FPGA. The challenge here is developing an algorithm to minimize the size of the LUT specifically and the FPGA, as a whole. Three SPWM designs are proposed in the project using the VHDL hardware descriptive language. Simulations are done using Mentor Graphic’s ModelSim SE 6.4 and the synthesis tool is Altera’s Quartus II Web Edition version 9.1. The proposed designs use two approaches, namely, the symmetrical properties of the sine wave to reduce the LUT size and also improvements in the programming codes to reduce the use of logic elements. Each of the proposed synthesized designs uses less than 40% of logic elements compared to the designs from previous works.