Study on threshold voltage shifts and reliability in PFETs by high-voltage on-state and off-state stress

Abstract

In recent decades, electronics have made much progress thanks to the scaling of silicon complementary metal-oxide-semiconductor (CMOS) very-large-scale integration (VLSI). Now, dimensions of state-of-the-art metal-oxide-semiconductor field effect transistors (MOSFETs) are as small as tens of nanometers. The size of MOSFETs in VLSI has been rapidly scaled down for more than forty years for higher performance, lower power consumption, and higher integration. In such aggressively scaled MOSFETs, the short-channel effects (SCEs) and variability have large impact on the behavior of devices, and other problems are arising. It is well known that the random variability of transistor characteristics is caused by the statistical nature of dopant atoms in the transistor channel which is called as random dopant fluctuation (RDF). The number and position of impurity atoms in the channel depletion layer in determining the threshold voltage of the transistor are randomly distributed. It is well known that the variability of transistor characteristics is one of the most critical challenges in VLSI. In particular, the instability in static random-access memory (SRAM) cells due to the variability of individual transistors in the cells is a serious problem that prevents further device integration and supply voltage lowering. Therefore, the analysis of cell unbalances at the transistor level, which leads to a severe yield loss of SRAM is needed for better understanding of SRAM stability at low VDD operation. Recently, a new concept of post-fabrication self-improvement technique of SRAM cell stability has been demonstrated. The self-improvement scheme in SRAM is used to improve cell stability after chip fabrication. This technique is simply applying stress voltage to the VDD node, when VDD is raised to high voltage, stronger pFET is stressed by ON-state stress, and Vth is increased and selectively weakened by self-improvement scheme indicating self-improvement mechanism works. On the other hand, the weaker pFET is stressed by OFF-state stress, and |Vth| is decreased and selectively strengthened by self-improvement scheme which is favorable for self-improvement technique. As a result SRAM cell stability is self-improved. In this work, experimental study on |Vth| shifts (the difference between |Vth| before stress and after stress) and reliability in pFETs by high voltage ON-state and OFF-state stress have been intensively done. Variability of |Vth| shifts (A|Vth|) in pFETs by high voltage ON-state and OFF-state stress for post-fabrication SRAM cell stability self-improvement technique has been experimentally investigated. It is found that sigma A|Vth| and mean A|Vth| have universal dependence. Large A|Vth| is better for self-improvement scheme, however, the sigma A|Vth| increases as A|Vth| increases. The magnitude of |Vth| shifts in pFETs by high voltage ON-state and OFF-state stress are also very important because it varies for different transistors. Some of the transistors has large |Vth| shift and some has small |Vth| shift. Experimental results show that |Vth| shifts in pFETs by high voltage ON-state and OFF-state stress are strongly dependent on process technology and transistor size. Recovery behaviors of |Vth| shifts in pFETs by high voltage ON-state and OFF-state stress for SRAM self-improvement technique are an important issue. After stress application, |Vth| shifted, however, after some relaxation time, |Vth| shift tend to move back to its initial state. Therefore, how much |Vth| shift is recover and how much remains (become permanent part) have been thoroughly discussed in this dissertation. After stress removal, there is a sudden recovery in a very short time. From long-time recovery measurements, it is found that the permanent part (A|Vth|) certainly exists even after 2 to 3 months relaxation period. It is newly found that |Vth| shifts in pFETs by high voltage ON-state and OFF-state stress for SRAM cell stability self-improvement technique has no critical recovery issue. One of the major concerns in SRAM self-improvement technique is the reliability issue. The transistors particularly pFETs are stressed by high voltage, and therefore, the reliability may be degraded. Hence, the reliability measurements of pFETs under the post-fabrication SRAM self-improvement technique have been performed. Negative Bias Temperature Instability (NBTI) degradation and NBTI lifetime estimation of pFETs under this technique are compared with fresh pFETs. It is found that although the NBTI lifetime of pFETs is slightly shortened by the application of self-improvement technique, the lifetime difference is just a little, indicating the self-improvement scheme has no critical reliability issues. In conclusion, the experimental study on |Vth| shifts in pFETs by ON-state and OFF-state stress for SRAM cell stability self-improvement scheme has been performed and their origins have been investigated through this study. The experimental results that have been obtained in this dissertation show important information on the |Vth| shifts and their variability behaviors in pFETs by high voltage ON-state and OFF-state stress for post-fabrication SRAM cell stability self-improvement scheme. It is found that the reliability of pFETs under this technique has no critical issues. This is an important step for the realization of this self-improvement technique. Post-fabrication technique will be essential in improving degraded yield of future large-scale SRAM with increased transistor variability.