Arithmetic logic unit design for silicon nanowire field-effect transistors logic

Abstract

As dimensions of conventional planar metal-oxide-semiconductor field effect transistor (MOSFET) are reduced, it cause a lot challenging issue such as short-channel effects (SCEs), scaling of gate oxide thickness and increase power consumption. Multigate such as double gate, tri-gate, surrounding gate and FinFET has been studied as potential structure to replace MOSFET. Thus this research report will describes the simulation and characterization of surrounded gate Silicon Nanowires Transistor (Si NWT). The cylindrical Gate-all around (GAA) Si NWT has showed robustness against SCE, ideal sub threshold swing, suppresses corner effect and suitable for low power devices. From this study simulation had proven that GAA Si NWT provides the best short channel device performance. Also highlighted in this research studies, to achieve symmetrical current in PMOS and NMOS, different number of nanowires channel is selected. Therefore by choosing large number of nanowires channel for PMOS transistor can help compensated the low value of hole mobility. In this work, 2:3 ratios of NMOS and PMOS channel of inverter had used as benchmark for ALU designed. Using the circuit modeling HSPICE, performance for Arithmetic Logic Unit (ALU) circuit in 30nm technology is analyzed with Silicon Nanowire (Si NW) compared with conventional planar MOSFET. The assessment of this circuit logic performance metric includes propagation delay, power-delay-product (PDP) and energy-delay-product (EDP) of full adder, XOR, AND and OR gate forming the ALU block. Moreover, ALU is built with less transistor count to implement Boolean expressions which help to reduced average power consumption, and delay.