Teoh, Chin Hong and Ismail, Razali (2006) Device design consideration for nanoscale MOSFET using semiconductor TCAD tools. In: Semiconductor Electronics, 2006. ICSE '06. IEEE International Conference, 29 Oct 2006-1 Dec 2006, Kuala Lumpur, Malaysia.
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Official URL: http://dx.doi.org/10.1109/SMELEC.2006.380770
The evolution of metal-oxide-semiconductor field effect transistor (MOSFET) technology has been governed mainly by device scaling over the past twenty years. One of the key questions concerning future ULSI technology is whether MOSFET devices can be scaled to 100 nmchannel length and beyond for continuing density and performance improvement. In this paper, the design, fabrication and characterization of high-performance and low-power 90 nm channel length MOSFET devices are described. Several parameters have to be scaled down such as gate oxide thickness, channel length, ion implantation for threshold voltage adjustment and other specifications to achieve desirable electrical characteristic. To control the short-channel effect (SCE) and hot-carrier reliability that limits device scaling, lightly doped drain (LDD) structure, shallow junction of drain / source and Shallow Trench Isolation (STI) are implemented. Virtual wafer fabrication (VWF) Silvaco TCAD Tools is used for fabrication and simulation of CMOS transistor namely ATHENA and ATLAS. Simulations using these programs provided the opportunity to study the effect of different device parameters on the overall device performance. The devices were simulated and gradually the performance of each one was improved, until an optimal device configuration was created for a particular application.
|Item Type:||Conference or Workshop Item (Paper)|
|Uncontrolled Keywords:||CMOS transistor, MOSFET device, Silvaco TCAD tool, channel length, complementary metal-oxide-semiconductor, computer aided design, device design consideration, device scaling, gate oxide thickness, hot-carrier reliability, ion implantation, lightly doped drain structure, metal-oxide-semiconductor field effect transistor, nanoscale MOSFET technology, optimal device configuration, semiconductor TCAD tool, shallow trench isolation, short-channel effect, threshold voltage adjustment, virtual wafer fabrication|
|Subjects:||T Technology > TK Electrical engineering. Electronics Nuclear engineering|
|Deposited By:||Norhafizah Hussin|
|Deposited On:||06 Jan 2009 06:37|
|Last Modified:||01 Jun 2010 15:52|
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