Wong, Yah Jin and Saad, Ismail and Ismail, Razali (2006) Characterization of strained silicon MOSFET using semiconductor TCAD tools. In: Semiconductor Electronics, 2006. ICSE '06. IEEE International Conference, 29 Oct 2006-1 Dec 2006, Kuala Lumpur, Malaysia.
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Official URL: http://dx.doi.org/10.1109/SMELEC.2006.380774
The paper is looking into the enhancement of conventional PMOS by incorporating a strained silicon within the channel and bulk of semiconductor. A detailed 2D process simulation of strained silicon PMOS (SSPMos) and its electrical characterization was done using TCAD tool. With the oxide thickness, Tox of 16 nm and germanium concentration of 35%, the threshold voltage Vt for the strained Si and conventional PMOS is -0.5067V and -0.9290V respectively. This indicates that the strained silicon had lower power consumption. Beside that, the drain induced barrier lowering (DIBL) value for the strained PMOS is 0.3034V and the conventional PMOS is 0.4747V, which shows a better performance for strained silicon as compared to conventional PMOS. In addition, the output characteristics were also obtained for SSPMos which showed an improvement of drain current compared with conventional PMOS.
|Item Type:||Conference or Workshop Item (Paper)|
|Uncontrolled Keywords:||2D process simulation, Si, drain current, drain induced barrier lowering, electrical characterization, semiconductor TCAD tools, strained silicon MOSFET, voltage 0.3034 V|
|Subjects:||T Technology > TK Electrical engineering. Electronics Nuclear engineering|
|Deposited By:||Norhafizah Hussin|
|Deposited On:||06 Jan 2009 05:02|
|Last Modified:||01 Jun 2010 15:52|
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