Characterization of planar and vertical n-channel mosfet in nanometer regime

Abstract

In recent years, there is more and more design on MOSFET that has been developed to fulfill the market need. This project focused on the comparison of planar and vertical n-channel MOS transistor characteristic with effective channel length of 100nm down to 50nm. Planar and vertical n-channel MOS transistors with effective channel length ranged from 50nm to 100nm has been developed. Simulation of the device design is done by using Silvaco-DevEdit. Short channel effect (SCE) is investigated through out the device simulation. SCEs affect on device and circuit performance in off-state leakage current and VT roll-off. At the device simulation process, using Silvaco Atlas, the electrical parameter is extracted to investigate the device characteristic. Several design analysis are performed to investigate the effectiveness and robustness of the method in order to prevent the varying threshold voltage or short channel effect of a MOSFET device. A single channel vertical NMOS shows better VT roll-off and better subthreshold swing at ~85mV/decade. On the other hand, planar NMOS has lower threshold voltage value which is suitable for low voltage devices. With these advantages from each NMOS analysis, one can decide which device to use to achieve required specification for specific usage in future.