Graph processing hardware accelerator for shortest path algorithms in nanometer very large-scale integration interconnect routing

Abstract

Graphs are pervasive data structures in computer science, and algorithms working with them are fundamental to the field. Many challenging problems in Very Large-Scale Integration (VLSI) physical design automation are modeled using graphs. The routing problems in VLSI physical design are, in essence, shortest path problems in special graphs. It has been shown that the performance of a graph-based shortest path algorithm can severely be affected by the performance of its priority queue. This thesis proposes a graph processing hardware accelerator for shortest path algorithms applied in nanometer VLSI interconnect routing problems. A custom Graph Processing Unit (GPU), in which a hardware priority queue accelerator is embedded, designed and prototyped in a Field Programmable Gate Array (FPGA) based hardware platform. The proposed hardware priority queue accelerator is designed to be parameterizable and theoretically cascadable. It is also designed for high performance and it exhibits a run-time complexity for an INSERT (or EXTRACT) queue operation that is constant. In order to utilize the high performance hardware priority queue module, modifications have to be made on the graph-based shortest path algorithm. In hardware, the priority queue size is constrained by the available logic resources. Consequently, this thesis also proposes a hybrid softwarehardware priority queue which redirects priority queue entries to software priority queue when the hardware priority queue module exceeds its queue size limit. For design validation and performance test purposes, a computationally expensive VLSI interconnect routing Computer Aided Design (CAD) module is developed. Results of the performance tests on the proposed hardware graph accelerator, graph computations are significantly improved in terms of algorithm complexity and execution speed.