Hardware core of pipelined thinning algorithm

Abstract

The process to associate a particular individual with an identity is known as personal recognition. One of the recognition system type is biometrics system. A biometric system is essentially a pattern recognition system that that performs authentication based on the individual’s behavioural or physiological characteristics. One of the method is finger vein biometrics, which is an authentication technique that identify individuals and verify identity based on the images of human finger veins beneath the skin. There are a lot of process involved in a complete biometrics system. One of the process is thinning. Thinning or skeletonization is a process that extracts the vein patterns from binary image and produces 1-pixel wide output binary image as the result. Existing biometrics system have their own weaknesses and drawbacks such as not showing "aliveness" and also easy to be tampered with. Moreover, software implementation of biometrics system usually performed in an insecure environment and biometrics template stored in a central server. This is insecure and can cause leakage of information. Furthermore, thinning is a time consuming process, which takes a very long time to be completed in software implementation. So the objective of this work is to design a dedicated hardware core for thinning algorithm, implement and enhance the existing algorithm for better hardware performance, and apply pipeline architecture to the hardware design to further speed-up thinning process. This work will implement the algorithm in software and hardware. Hardware implementation of the algorithm is compared with software implementation in terms of accuracy and performance (speed). The hardware core designed managed to achieve a significant improvement in processing time. The work done in this project also managed to map a complex algorithm into hardware implementation and is the first one to implement thinning hardware design using System Verilog.