Network-on-chip fault detection and router self-test

Abstract

Network-on-Chip (NoC) router is an entity that facilitates communication between subsystem or IP cores on an integrated circuit. Faults such as permanent fault, transient fault and random fault are commonly observed on a NoC router. They may severely impact the functionality of an NoC router if not handled appropriately. This project proposes a mechanism to identify error and perform self-testing in NOC router by enhancing the Register Transfer Level (RTL) design of CONNECT NoC Baseline Router with error detection mechanism, as well as devising a built in selftest mode for NOC router. Both proposed error detection mechanism and built in self-test mode have been successfully implemented using System Verilog. The work presented in this project shows possible enhancement to NoC router architecture to detect erroneous packets. NoC router is able to detect faults through proposed error dection tecchniques. This allows router self-test in order to sustain the functionality of a system in the presence of faults. Simulation results show that additional logics do not affect NoC router performance