Hardware-accelerated localization for automated license plate recognition system

Abstract

Automatic License Plate Recognition (ALPR) is a continuous process of extracting license plate information from a series of input images. Localization is an imperative stage in ALPR system because it extracts the sub image which contains the potential license plate for subsequent processing. Many ALPR systems are designed to operate on general purpose processor, in which the low degree of instruction and data level parallelism is not maximized, resulting in lower efficiency. Also, current ALPR system in the market is not modular and generalized to cater license plates from different nations with different languages and standards. This project proposes a multi-feature extraction algorithm for license plate localization catering various plate and environment variation factors, as well as hardware architecture to implement the algorithm with full modularity baseline. The proposed hardware architecture has been successfully modelled and implemented using System Verilog. It achieves an average speed up of 222x across different test images compared to software-based algorithm and 100% matching the localization accuracy in software.