Advanced encryption standard (AES) coprocessor

Abstract

The purpose of this project is to design a high throughput Advanced Encryption Standard (AES) coprocessor using SystemVerilog Hardware Description Language (HDL). AES coprocessor has been widely used to offload the compute intensive cryptography tasks from the main processor due to its efficiency and performance compare to the pure software solution. Conventional AES core design using iterative loop approach is not optimized for high throughput operation. Therefore pipelined architecture is the most recommend method for high throughput design. However most of the high throughput designs tend to reliance on vendor specific features to boost the performance. This has caused the design becomes non-generic and low portability. A bottom-up approach has being used to design the coprocessor. A non-pipelined AES coprocessor was being built first as the baseline design. Then different types of pipelined implementation were being explored for possible adoption. The throughput, size and potential enhancement are the main criteria being evaluated. It was discovered that the Full Outer-Round pipelined architecture is the most efficient design in term of throughput and size. From the analysis of the Full Outer-Round pipelined model, a novel method called Single Datapath Dual Output (SDDO) has been proposed to double the throughput of the pipelined coprocessor. Simulation results demonstrated that SDDO architecture is able to double the throughput of the pipelined design while only requires 7% of additional resource to implement.