Design of a neural network for FPGA implementation

Abstract

Very often complex transfer functions are needed to be implemented in ASIC for faster or real-time application. Other than implementing a transfer function according to its equation or algorithm, prediction method can be used in certain application where accuracy can be tolerated. In this project, application of neural network as a predictor is studied. Focus will be placed on back-propagation feed-forward neural network and its realization in hardware using Verilog Hardware Descriptive Language (HDL). Hardware design challenges like hardware resource utilization, throughput of various design approaches were explored. Main objective of this project is to produce a high throughput reconfigurable back propagation neural network hardware module that can be applied or integrated into bigger hardware system. Altera Quartus II and ModelSim-Altera CAD tool was used as logic synthesizing tool and hardware simulation tool, respectively, to achieve abovementioned objective. MATLAB was also being used to model neural network in software which served as a benchmark for hardware design. Multi-cycle design approach successfully reduces resource utilization on hardware-intensive neural network module, while pipelining the design helped to achieve a high-throughput design. Utilization of RAM for reconfiguration purpose greatly reduced throughput of the design due to the fact that only one weight or bias values are loaded in every clock cycle.