A high speed 2D convolution hardware module for image processing applications in hardware

Abstract

Visual information plays an essential role in almost all areas of our life, hence making image processing a very important subject of research. Image processing can be divided into digital image processing and analog image processing. Various applications including video surveillance, target recognition, and image enhancement requires digital image processing. In such applications, for functions like image filtering, image restoration, object tracking, template matching and many others, the spatial domain two-dimensional (2D) convolution plays a pivotal role. These functions are usually implemented in software previously but are slowly moving towards hardware for speed, as hardware allows pipelining and parallelism. The main objective of this project is to develop an image processing algorithm, 2D convolution. This project starts with architecture definition, followed by design implementation, verification and burning the design on FPGA. At the architecture definition stage, two different datapaths architectures are explored, Barrel Shifter and Multiplier. Basic design specifications are set and then design implementation is pursued. Verilog HDL is used to code the design; Quartus II tool is used for compilation and synthesis. The functionality and timing of the design is then verified using Modelsim tool before bringing the design to FPGA and tested using Quartus II’s SignalTapII Logic Analyzer. Additionly, the design is further verified with real image pixels and compared the output pixels with that obtained from software (MATLAB). Altera Quartus II compilation report shows the 2D convolution design with Barrel Shifter can run at higher frequency compared to multiplier, and the design with off chip RAM runs faster than the design with on chip RAM.