A 10-bit 50 mega-samples-per-second pipelined analog-to-digital converter

Abstract

Most of modern communication devices are implemented on portable systems powered by a battery with limited energy. Due to their dependence on batteries, some efforts have to be made to minimize the power consumption of these devices. One of the approaches is to use low power analog-to-digital converter (ADC). This thesis focuses on the design implementation of low power pipelined ADC for wireless communication system. The pipelined ADC was realized using 1.5-bit per-stage structures with digital error correction. For power reduction, dedicated front-end sample-and-hold circuit used in conventional pipelined ADC architecture is removed. Furthermore, power analysis has been performed using MATLAB® to assist in determining the best stage resolution in pipelined stages. A dynamic comparator is employed to optimize further the power consumption in pipelined stages. This low power pipelined ADC is implemented using Siltera’s 0.18µm, 1.8-3.3V complementary metal oxide semiconductor process, with double layer poly-silicon and five metal layers. The designed pipelined ADC exhibits a 10-bit resolution at 50 Mega-Sample per-second and 50.82dB signal to noise and distortion ratio with an effective number of bits of 8.15-bit. The differential non-linearity (DNL) and the integral non-linearity (INL) are ±1 least-significant of bits (LSB). The power consumption is 97mW from a 3V supply and the entire area of the pipelined ADC including input and output pads is 2.4mm2.