Study on FPGA based IIR filter using quantitative approach

Abstract

The main goal of this project is to design a digital filter which is compatible between simulation tool (software) and hardware implementation using Matlab and Quartuss II. The filter is realized in Direct Form II biquad architecture to achieve scalable and expandable design which can be cascaded if necessary. Filter quantization procedure is presented based on the finite word-length arithmetic to determine the bit length of the filter’s digital parameters as accurate as possible. With the resulting bit-true model, hardware design implementation using Verilog RTL for Altera FPGA is then performed. A biquad filter in FPGA, using numerous hardware realization methods, namely fully combinational, combinational-sequential and bit serial are designed and performance analysis is carried out by comparing their efficiency and area. The design is then optimized further to be more cost-effective by implementing the bit-serial arithmetic architecture where multipliers are replaced with lookup table (LUT). According to the simulation result, fully-combinational is the fastest and the most expensive approach with unconstrained resource utilization while combinational-sequential compromises between area and speed with limited resources. On the other hand, bit-serial model achieves highest maximum frequency with lowest propagation delay between registers. Optimization with LUT usage is a hybrid model of fully-combinational and bit-serial which it balances up the pros and cons by improving the maximum frequency of fully combinational and reducing the total execution time of bit-serial approach.