Reconfigurable address generation unit for 2D correlation in FPGA

Abstract

2D correlation has been commonly used in image processing. In general, performance of the 2D correlation function depends on its processing speed, memory speed as well as address calculation speed. As the processing and memory speed increase, the address calculation speed becomes bottleneck for overall performance. It is thus necessary to accelerate the address calculation or generation by implementing it in hardware like FPGA rather than depending on software to calculate the addresses; such hardware is known as address generation unit (AGU). Prior arts of reconfigurable AGU can be reconfigured to generate address for different digital signal processing (DSP) functions including 2D correlation; however, they don’t support address generation for different designs of 2D correlation circuits. None of the prior arts of AGU able to handle image edge condition while considering data reuse in 2D correlation circuit. Furthermore, prior arts of AGU have never been implemented in FPGA. In this paper, a reconfigurable AGU for different designs of 2D correlation in FPGA, which takes care of image edge condition while considering data reuse, is presented. The proposed reconfigurable AGU is targeted for two different architectures of 2D correlation circuit. The two architectures of 2D correlation circuit, which work together with the reconfigurable AGU, are also designed. The proposed reconfigurable AGU reduces the circuit area by sharing or reusing the common components such as adder, comparator, register and etc. In general, the reconfigurable AGU reduces circuit area by 30% as compared to integrating two dedicated AGUs for two different architectures of 2D correlation circuit. The maximum speed of the reconfigurable AGU is 125MHz for Cyclone III device targeting FPGA.