Chia, Ie Chen (2012) Floorplaning methodology for network on chip. Masters thesis, Universiti Teknologi Malaysia, Faculty of Electrical Engineering.
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| Item Type: | Thesis (Masters) |
|---|---|
| Additional Information: | Thesis (Sarjana Kejuruteraan (Elektrik - Komputer dan Sistem Mikroelektronik)) - Universiti Teknologi Malaysia, 2012; Supervisor : Dr. Muhammad Nadzir Marsono |
| Subjects: | Unspecified |
| Divisions: | Electrical Engineering |
| ID Code: | 32097 |
| Deposited By: | Kamariah Mohamed Jong |
| Last Modified: | 12 Jun 2013 07:54 |
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