Cheng, Chen Kong (2009) System-on-chip (SoC) testing using adhoc high-level design for-testability method. Masters thesis, Universiti Teknologi Malaysia, Faculty of Electrical Engineering.
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The design of System-on-Chip (SoC) is becoming more complex and number of transistors in a chip has increased from millions of gates to billions of gates nowadays but the number of Input/Output pins still remains about the same. In this case, design-for-test (DFT) becomes so important in order to make the chip more easily testable. By increasing the DFT features into a chip, this will definitely increase the overhead of the chip. In this project, an alternative DFT method is used to minimize the overhead of the chip resulted from DFT without affecting the fault coverage. A case study is conducted by applying the proposal ad-hoc DFT method on GCD calculator. Area overhead and test application clock cycles are evaluated and compared to those parameters resulted from the conventional DFT method called full scan. The case study showed that the area overhead was smaller and the test application clock cycles were less when GCD was augmented with proposed DFT method.
|Item Type:||Thesis (Masters)|
|Additional Information:||Thesis (Sarjana Kejuruteraan (Komputer dan Sistem Mikroelektronik)) - Universiti Teknologi Malaysia, 2009; Supervisor : Dr. Ooi Chia Yee|
|Uncontrolled Keywords:||systems on a chip, testing, design-for-test (DFT) methods|
|Subjects:||T Technology > TK Electrical engineering. Electronics Nuclear engineering|
|Deposited By:||Kamariah Mohamed Jong|
|Deposited On:||08 Aug 2012 00:51|
|Last Modified:||08 Aug 2012 00:57|
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